With increasing demands for embedded memory type structures, mixed-signal circuits, and system on chip (SOC) IC design, it has become necessary to form multiple transistor structures on a single die to achieve integrated functioning of the different transistor structures. For example, transistors with different structures and functions typically operate under different current and voltage parameters requiring different LDD widths and depths for the various transistors. The width of the LDD region is typically controlled by the width of spacers formed adjacent to a semiconductor gate structure to act as a mask before or following one or more doping processes, for example ion implantation, to form regions of differing doping concentrations, for example source/drain (S/D) regions adjacent the LDD regions.
Although methods have been proposed in the prior art for forming multiple width sidewall spacers, the methods generally require an excessive number of photoresist patterning processes and etching processes and/or deposition processes to form gate sidewall spacers of different widths for different transistor designs formed on a single wafer or die.
Thus, there is a need in the semiconductor manufacturing art for an improved method for forming sidewall spacers of multiple widths including a reduced number of processing steps.
It is therefore an object of the invention to provide an improved method for forming sidewall spacers of multiple widths including a reduced number of processing steps while overcoming other shortcomings and deficiencies of the prior art.